Welcome

TAPA is a task-parallel HLS framework that compiles C++ dataflow programs to Verilog RTL for Xilinx FPGAs, with software simulation requiring no FPGA hardware.

C++ source → tapa compile → RTL (.xo) → Vitis v++ → FPGA bitstream

Choose your path

• New to FPGA? → Your First Run
• Migrating from Vitis HLS? → Lab 3: Migrating from Vitis HLS
• Already know FPGA? → How-To Guides (start with software simulation)

Most common tasks

• Installation
• Your First Run
• Fast Hardware Simulation
• Build & Deploy xclbin
• Debug a Deadlock

Next step: Installation