2. Getting Started
  3. Welcome
  4. Installation
  5. Your First Run
  6. Your First Debug Cycle
  7. Full FPGA Compilation
  9. How TAPA Works
  10. The Programming Model
  11. The Compile Pipeline
  12. Tasks
  13. Streams
  14. Memory Access: mmap
  15. Memory Access: async_mmap
  17. How-To Guides
  18. Software Simulation
  19. Fast Hardware Simulation
  20. Parallel RTL Emulation
  21. Vitis Cosimulation
  22. Build & Run on Board
  23. Remote Execution
  24. Using the Visualizer
  25. Performance Tuning
  27. Tutorials
  28. Learning Path
  29. Lab 1: Vector Add
  30. Lab 2: High-Bandwidth Memory
  31. Lab 3: Migrating from Vitis HLS
  32. Lab 4: Custom RTL Modules
  33. Lab 5: Parallel RTL Emulation
  34. Lab 6: Floorplan & DSE
  35. Examples Catalog
  37. Troubleshooting
  38. Common Errors
  39. Deadlocks & Hangs
  40. Cosimulation Issues
  42. Reference
  43. CLI Commands
  44. Runtime Flags
  45. C++ API
  46. Output Files
  47. C++ Quick Reference
  48. Publications
  49. Glossary
  51. Developer Guide
  52. Building from Source
  53. Development Workflow
  54. Contributing
  55. Release Process